EDJ1104BBSE Datasheet, PDF (63/151 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Clock Jitter [DDR3-1600, 1333]
-GL, -GN
-DG, -DJ
Data rate (Mbps)
1600
1333
Parameter
Symbol
min.
max.
min.
max.
Unit Notes
Average clock period
tCK (avg) 1250
3333
1500
3333
ps 1
tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max
Absolute clock period
tCK (abs)
+
+
+
tJIT(per)min tJIT(per)max tJIT(per)min
Clock period jitter
tJIT (per)
−70
70
−80
Clock period jitter during
DLL locking period
tJIT (per, lck) −60
60
−70
Cycle to cycle period Jitter
tJIT (cc)

140

ECycle to cycle clock period jitter
during DLL locking period
tJIT (cc, lck)

120

Cumulative error across 2
cycles
tERR (2per) −103
103
−118
Cumulative error across 3
O_cycles
tERR (3per) −122
122
Cumulative error across 4
cycles
tERR (4per) −136
136
−140
−155
Cumulative error across 5
L ^cycles
tERR (5per) −147
147
−168
+
ps
tJIT(per)max
80
ps
70
ps
160
ps
140
ps
118
ps
140
ps
155
ps
168
ps
2
6
6
7
7
8
8
8
8
Cumulative error across 6
cycles
Cumulative error across 7
cycles
Cumulative error across 8
cycles
Cumulative error across 9
cycles
Cumulative error across 10
cycles
Cumulative error across 11
cycles
Cumulative error across 12
cycles
Cumulative error across
n = 13, 14…49, 50 cycles
Average high pulse width
Average low pulse width
Absolute clock high pulse width
Absolute clock low pulse width
Duty cycle jitter
tERR (6per) −155
155
−177
177
tERR (7per) −163
163
−186
186
tERR (8per) −169
169
−193
193
P^{tERR (9per) −175}
175
−200
200
tERR (10per) −180
180
−205
205
tERR (11per) −184
184
−210
210
r_{tERR (12per) −188}
188
−215
215
o _{tERR (nper)}
tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min
tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max
tCH (avg) 0.47
0.53
0.47
0.53
d ^{tCL (avg)}
0.47
0.53
0.47
0.53
tCH (abs) 0.43

0.43

tCL (abs)
0.43

uct _{tJIT (duty) }

0.43



ps 8
ps 8
ps 8
ps 8
ps 8
ps 8
ps 8
ps 9
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
ps
3
4
10, 11
10, 12
5
Data Sheet E1375E50 (Ver. 5.0)
63