EDJ1104BBSE Datasheet, PDF (1/151 Pages) Elpida Memory – 1G bits DDR3 SDRAM

DATA SHEET
1G bits DDR3 SDRAM
EEEDDDJJJ111111001486BBBBBBSSSEEE (((21652468MMMwwwooordrrddsss_{×××1648} bbbiiitttsss))) _{Specifications}
E• Density: 1G bits
• Organization
 32M words × 4 bits × 8 banks (EDJ1104BBSE)
 16M words × 8 bits × 8 banks (EDJ1108BBSE)
O^{ 8M words × 16 bits × 8 banks (EDJ1116BBSE)}
• Package
 78-ball FBGA (EDJ1104/1108BBSE)
 96-ball FBGA (EDJ1116BBSE)
L ^{ Lead-free (RoHS compliant) and Halogen-free}
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Power supply: VDD, VDDQ = 1.5V ± 0.075V
• Data rate
 1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)
• 1KB page size (EDJ1104/1108BBSE)
 Row address: A0 to A13
P  Column address: A0 to A9, A11 (EDJ1104BBSE)
A0 to A9 (EDJ1108BBSE)
• 2KB page size (EDJ1116BBSE)
 Row address: A0 to A12
 Column address: A0 to A9
r _{• Eight internal banks for concurrent operation}
• Interface: SSTL_15
o _{• Burst lengths (BL): 8 and 4 with Burst Chop (BC)}
• Burst type (BT):
 Sequential (8, 4 with BC)
 Interleave (8, 4 with BC)
d _{• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11}
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
u _{• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)}
• Refresh: auto-refresh, self-refresh
• Refresh cycles
c  Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
t ^{• Operating case temperature range}
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
 Synchronous ODT
 Dynamic ODT
 Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read
out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset
function
• SRT range:
 Normal/extended
• Programmable Output driver impedance control
 TC = 0°C to +95°C
Document No. E1375E50 (Ver. 5.0)
Date Published April 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in June, 2010.
Elpida Memory, Inc. 2008-2009