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EBE21UE8AADA Datasheet, PDF (6/21 Pages) Elpida Memory – 2GB DDR2 SDRAM SO-DIMM
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EBE21UE8AADA
Byte No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47 to 61
62
63
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Minimum active to precharge time
(tRAS)
-5C
-4A
0 0 1 0 1 1 0 1 2DH
0 0 1 0 1 0 0 0 28H
Module rank density
0 0 0 0 0 0 0 1 01H
Address and command setup time
before clock (tIS)
-5C
0 0 1 0 0 1 0 1 25H
-4A
0 0 1 1 0 1 0 1 35H
Address and command hold time after
clock (tIH)
0 0 1 1 1 0 0 0 38H
-5C
-4A
0 1 0 0 1 0 0 0 48H
Data input setup time before clock
(tDS)
-5C
0 0 0 1 0 0 0 0 10H
-4A
0 0 0 1 0 1 0 1 15H
Data input hold time after clock (tDH)
-5C
0 0 1 0 0 0 1 1 23H
-4A
0 0 1 0 1 0 0 0 28H
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
Internal write to read command delay
(tWTR)
0 0 0 1 1 1 1 0 1EH
-5C
-4A
0 0 1 0 1 0 0 0 28H
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
-5C
0 0 1 1 1 1 0 0 3CH
-4A
0 0 1 1 0 1 1 1 37H
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
1
1
1
1
1
7FH
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
Dout to DQS skew
-5C
0 0 0 1 1 1 1 0 1EH
-4A
0 0 1 0 0 0 1 1 23H
Data hold skew (tQHS)
-5C
0 0 1 0 1 0 0 0 28H
-4A
0 0 1 0 1 1 0 1 2DH
PLL relock time
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 0 00H
SPD Revision
Checksum for bytes 0 to 62
-5C
-4A
0 0 0 1 0 0 1 0 12H
0 1 1 0 0 1 0 1 65H
1 1 0 1 1 1 1 1 DFH
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
66
Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Comments
45ns
40ns
1G bytes
0.25ns*1
0.35ns*1
0.38ns*1
0.48ns*1
0.10ns*1
0.15ns*1
0.23ns*1
0.28ns*1
15ns*1
7.5ns*1
10ns*1
7.5ns*1
TBD
Undefined
60ns*1
55ns*1
127.5ns*1
8ns*1
0.30ns*1
0.35ns*1
0.40ns*1
0.45ns*1
Undefined
Rev. 1.2
Continuation
code
Elpida Memory
Preliminary Data Sheet E0767E10 (Ver. 1.0)
6
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