EDE5108AGBG Datasheet, PDF (54/74 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5108AGBG
Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the
implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in
a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used
during read cycles.
DQS
/DQS
DQ
T1
T2
T3
in in
in in
T4
T5
Tn
in in in in
in
DM
[tDQSS(min.)]
/CK
CK
Command
WRIT
DQS, /DQS
DQ
DM
[tDQSS(max.)]
DQS, /DQS
DQ
DM
Write mask latency = 0
Data Mask Timing
tWR
NOP
WL
tDQSS
in0
in2 in3
WL
tDQSS
in0
in2 in3
Function, WL = 3, AL = 0 shown
Data Mask
Data Sheet E0917E30 (Ver. 3.0)
54