EDE5132AABG Datasheet, PDF (51/74 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5132AABG
Burst Write Command [WRIT]
The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of
the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read
latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble)
one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge
of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent
burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst
has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst
write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery
time (tWR).
T0
T1
T2
T3
T4
T5
T6
T7
T9
/CK
CK
Command
WRIT
NOP
≤ tDQSS
PRE
NOP
ACT
DQS, /DQS
WL = RL –1 = 2
DQ
in0 in1 in2 in3
≥tWR
≥tRP
Completion of
the burst write
Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))
T0
T1
/CK
CK
Command
WRIT
DQS, /DQS
DQ
WL = RL –1 = 2
T2
T3
T4
T5
T6
NOP
≤ tDQSS
in0 in1 in2 in3 in4 in5 in6 in7
T7
T8
T9
T11
PRE
NOP
ACT
≥tWR
≥tRP
Completion of
the burst write
Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))
Preliminary Data Sheet E1115E40 (Ver. 4.0)
51