HM5259165B Datasheet, PDF (50/63 Pages) Elpida Memory – 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

HM5259165B/HM5259805B/HM5259405B-75/A6
AC Characteristics (Ta = 0 to +70˚C, V_CC, V_CCQ = 3.3 V ± 0.3 V, V_SS, V_SSQ = 0 V)
Parameter
PC/100
Symbol Symbol
System clock cycle time
(CAS latency = 2)
t _CK
Tclk
(CAS latency = 3)
t _CK
Tclk
CLK high pulse width
t _CKH
Tch
CLK low pulse width
t _CKL
Tcl
Access time from CLK
(CAS latency = 2)
(CAS latency = 3)
t _AC
Tac
t _AC
Tac
Data-out hold time
t _OH
Toh
CLK to Data-out low impedance t_LZ
CLK to Data-out high impedance t_HZ
(CAS latency = 2, 3)
Input setup time
CKE setup time for power down
exit
t_AS, t_CS, t_DS, Tsi
t _CES
t _CESP
Tpde
Input hold time
Ref/Active to Ref/Active
command period
t_AH, t_CH, t_DH, Thi
t _CEH
t _RC
Trc
Active to Precharge command t_RAS
period
Tras
Active command to column
t _RCD
command (same bank)
Trcd
Precharge to active command t_RP
Trp
period
Write recovery or data-in to
t _DPL
Tdpl
precharge lead time
Active (a) to Active (b) command t_RRD
Trrd
period
Transition time (rise and fall)
t_T
Refresh period
t _REF
HM5259165B/
HM5259805B/
HM5259405B
-75
-A6
Min Max Min
10
—
10
7.5
—
10
2.5
—
3
2.5
—
3
—
6
—
—
5.4
—
2.7
—
3
2
—
2
—
5.4
—
1.5
—
2
1.5
—
2
0.8
—
1
67.5 —
70
45
120000 50
20
—
20
20
—
20
15
—
20
15
—
20
1
5
1
—
32
—
Max Unit Notes
—
ns 1
—
ns
—
ns 1
—
ns 1
6
ns 1, 2
6
ns
—
ns 1, 2
—
ns 1, 2, 3
6
ns 1, 4
—
ns 1, 5, 6
—
ns 1
—
ns 1, 5
—
ns 1
120000 ns 1
—
ns 1
—
ns 1
—
ns 1
—
ns 1
5
ns
32
ms
Data Sheet E0118H10
50