MC-4R128FKK6K Datasheet, PDF (5/13 Pages) Elpida Memory – 128MB 32-bit Direct Rambus DRAM RIMM Module

MC-4R128FKK6K
Signal
Module
connector pads
I/O
ROW2_THRU_R..
ROW0_THRU_R
A52, B50, A50
I
SCK_THRU_L
A2
I
SCK_THRU_R
A71
I
SIN_THRU
B34
I/O
SOUT_THRU
A34
I/O
CFM_TERM
B103
I
CFMN_TERM
B101
I
CMD_TERM
COL4_TERM..
COL0_TERM
CTM_TERM_L
A115
I
B97, A97, B95, A95,
B93
I
B73
I
CTM_TERM_R
A103
I
CTMN_TERM_L B71
I
CTMN_TERM_R A105
I
DQA8_TERM..
DQA0_TERM
DQB8_TERM..
DQB0_TERM
ROW2_TERM..
ROW0_TERM
B113, A113, B111,
A111, B109, A109, I/O
B107, A107, B105
A85, B85, A87, B87,
A89, B89, A91, B91, I/O
A93
A101, B99, A99
I
SCK_TERM
B115
I
SIN_TERM
VTERM
B83
I/O
A60, B60, A61, B61
Type
RSL
VCMOS
VCMOS
VCMOS
VCMOS
RSL
RSL
VCMOS
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
VCMOS
VCMOS
Description
Row bus. 3-bit bus containing control and address information
for row accesses. Connects to right RDRAM device on "Thru"
Channel.
Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.
Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.
"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of right RDRAM device on
"Thru" Channel.
"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO1 of left RDRAM device on
"Thru" Channel.
Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Term" Channel.
"Term" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Term" Channel.
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
"Term" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Term” Channel. Connects to right RDRAM device on
"Term" Channel. DQA8_TERM is non-functional on modules.
"Term" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Term” Channel. Connects to right RDRAM device on
"Term" Channel. DQB8_TERM is non-functional on modules.
"Term" Channel Row bus. 3-bit bus containing control and
address information for row accesses. Connects to right
RDRAM device on "Term" Channel.
Serial Clock input. Clock source used to read from and write
to "Term" Channel RDRAM control registers. Connects to
right RDRAM device on "Term" Channel.
"Term" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of left RDRAM device on
"Term" Channel.
"Term" Channel Termination voltage.
Preliminary Data Sheet E0269N10 (Ver. 1.0)
5