EDD2516AKTA Datasheet, PDF (5/49 Pages) Elpida Memory – 256M bits DDR SDRAM

EDD2516AKTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max.
Parameter
Symbol
Grade
× 16
Unit
Test condition
Notes
Operating current (ACT-PRE) IDD0
-6B
110
-7A, -7B 100
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACT-READ-PRE)
IDD1
-6B
140
-7A, -7B 130
CKE ≥ VIH, BL = 4,
mA
CL = 2.5,
tRC = tRC (min.)
Idle power down standby
current
IDD2P
3
mA
CKE ≤ VIL
Floating idle standby current IDD2F
-6B
35
-7A, -7B 30
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
E^{Quiet idle standby current}
IDD2Q
-6B
30
-7A, -7B 25
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
Active power down standby
current
IDD3P
20
mA
CKE ≤ VIL
O^{Active standby current}
IDD3N
-6B
55
-7A, -7B 50
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
Operating current
(Burst read operation)
IDD4R
-6B
205
-7A, -7B 180
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
Operating current
(Burst write operation)
IDD4W
-6B
205
-7A, -7B 180
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
L ^{Auto Refresh current}
IDD5
-6B
200
-7A, -7B 175
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Self refresh current
IDD6
3
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Operating current
(4 banks interleaving)
IDD7A
-6B
350
-7A, -7B 300
mA
BL = 4
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
P _{2. One bank operation.}
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
r _{6. DQ, DM and DQS transition twice per one clock cycle.}
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
o 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
d ^{DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)}
Parameter
Input leakage current
u ^{Output leakage current}
Output high current
ct ^{Output low current}
Symbol
ILI
ILO
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
—
—
Unit
Test condition
µA
VDD ≥ VIN ≥ VSS
µA
VDDQ ≥ VOUT ≥ VSS
mA
VOUT = 1.95V
mA
VOUT = 0.35V
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
5, 6, 7
Note
Preliminary Data Sheet E0303E40 (Ver. 4.0)
5