EDD2516AKTA Datasheet, PDF (1/49 Pages) Elpida Memory – 256M bits DDR SDRAM

PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2516AKTA (16M words × 16 bits) _Description
The EDD2516AKTA is a 256M bits Double Data Rate
(DDR) SDRAM organized as 4,194,304 words × 16 bits
× 4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
Espeed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
O^{the on-chip Delay Locked Loop (DLL) can be set}
enable or disable. It is packaged in 66-pin plastic
TSOP (II).
Features
• Power supply : VDDQ = 2.5V ± 0.2V
L_{: VDD = 2.5V ± 0.2V}
• Data rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
P _{the receiver}
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
r • DQS is edge aligned with data for READs; center
aligned with data for WRITEs
o ^{• Differential clock inputs (CK and /CK)}
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
d _{• Data mask (DM) for write data}
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
u ^{• Programmable burst length (BL): 2, 4, 8}
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
c _{⎯ 7.8μs maximum average periodic refresh interval}
• 2 variations of refresh
t ^{⎯ Auto refresh}
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
NC 14
VDDQ 15
LDQS 16
NC 17
VDD 18
NC 19
LDM 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
⎯ Self refresh
VDDQ
VSSQ
Power for DQ circuit
Ground for DQ circuit
NC
No connection
Document No. E0303E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2002-2005