ECS2532JECN-A Datasheet, PDF (45/48 Pages) Elpida Memory – 256M bits SDRAM Bare Chip

ECS2532JECN-A
Self Refresh Cycle
CLK
CKE
CKE Low
lSREX
/CS
/RAS
/CAS
/WE
BS
Address
A10=1
E ^DQM
DQ (input)
DQ (output)
t RP
Precharge command
O^{If needed}
Self refresh entry
command
L ^{Clock Suspend Mode}
High-Z
t RC
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
t RC
Next ^Auto
clock ^refresh
enable
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
BL = 4
= VIH or VIL
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
012
R:a
Bank0 Active clock
Active suspend start
R:a
Bank0 Active clock
Active suspend start
3
tSI
tHI
tSI
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
P ^{= VIH or VIL}
C:a
R:b
C:b
r_{a a+1 a+2}
a+3
b b+1 b+2 b+3
High-Z
Active clock Bank0
o suspend end Read
Bank3 Read suspend Read suspend Bank3 Bank0
Active
start
end Read Precharge
Earliest Bank3
Precharge
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
d _{C:a R:b}
C:b
u ^High-Z
a a+1 a+2
a+3 b b+1 b+2 b+3
Active clock Bank0 Bank3 Write suspend Write suspend Bank3 Bank0
ct ^{supendend Write Active}
start
end Write Precharge
Earliest Bank3
Precharge
Data Sheet E0698E50 (Ver. 5.0)
45