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ECS2532JECN-A Datasheet, PDF (1/48 Pages) Elpida Memory – 256M bits SDRAM Bare Chip | |||
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DATA SHEET
256M bits SDRAM Bare Chip
ECS2532JECN-A (8M words à 32 bits) Specifications
⢠Density: 256M bits
⢠Organization
 2M words à 32 bits à 4 banks
E⢠Package: Bare chip
⢠Power supply: VDD, VDDQ = 2.5V ± 0.2V
⢠Clock frequency: 133MHz (max.)
⢠2KB page size
O Row address: A0 to A11
 Column address: A0 to A8
⢠Four internal banks for concurrent operation
⢠Interface: LVCMOS
⢠Burst lengths (BL): 1, 2, 4, 8, full page
L ⢠Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
 Interleave (1, 2, 4, 8)
⢠/CAS Latency (CL): 2, 3
⢠Precharge: auto precharge option for each burst
P access
⢠Driver strength: half/quarter
⢠Refresh: auto-refresh, self-refresh
⢠Refresh cycles: 4096 cycles/64ms
r  Average refresh period: 15.6µs
⢠Operating ambient temperature range
oduct  TA=0°Cto+70°C
Features
⢠Ã32 organization
⢠Single pulsed /RAS
⢠Burst read/write operation and burst read/single write
operation capability
⢠Byte control by DQM
Document No. E0698E50 (Ver. 5.0) This product became EOL in September, 2007.
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006
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