EDS1232CASE Datasheet, PDF (44/53 Pages) Elpida Memory – 128M bits SDRAM (4M words x 32 bits)

EDS1232CASE
Write Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
A10
Address
DQM
DQ (input)
DQ (output)
tCK
tCH tCL
VIH
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tRAS
tRC
tRP
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI
tHI
tSI t HI tSI tHI tSI tHI tSI tHI
tDPL
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
Mode Register Set Cycle
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VIH
valid
code
R: b
C: b
C: b’
lRP
Precharge
If needed
Mode
register
Set
lMRD
Bank 3
Active
lRCD
High-Z
Bank 3
Read
b
Output mask
b+3 b’ b’+1 b’+2 b’+3
lRCD = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0351E30 (Ver. 3.0)
44