EDE5104ABSE Datasheet, PDF (42/66 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Enabling a read command at every other clock supports the seamless burst read operation. This operation is
allowed regardless of same or different banks as long as the banks are activated.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
/CK
CK
Command
DQS, /DQS
READ
A
NOP
READ
B
NOP
DQ
RL = 4
out out out out out out out out out out out out
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Burst interrupt is only
allowed at this timing.
Burst Read Interrupt by Read
Notes :1. Read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another read command. Read burst interruption by write
command or precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous read command. any other read burst
interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with auto precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another read with auto precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, minimum read to precharge timing is AL + BL/2 where BL is the burst length
set in the mode register and not the actual burst (which is shorter because of interrupt).
Data Sheet E0323E90 (Ver. 9.0)
42