EDE5104ABSE Datasheet, PDF (3/66 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Pin Configurations
/xxx indicates active low signal.
64-ball FBGA (µBGA)
(×8, ×4 organization)
1
2
3
7
8
9
A
NC NC
B
NC NC
C
D
E
VDD NU/ /RDQS VSS
(NC)*
F
DQ6
(NC)*
VSSQ
DM/RDQS
(DM)*
G
VDDQ DQ1 VDDQ
H
DQ4
(NC)*
VSSQ
DQ3
J
VDDL VREF VSS
K
CKE /WE
L
NC BA0 BA1
M
A10 A1
N
VSS A3 A5
P
A7 A9
R
VDD A12 NC
VSSQ /DQS VDDQ
DQS
VSSQ
DQ7
(NC)*
VDDQ DQ0 VDDQ
DQ2
VSSQ
DQ5
(NC)*
VSSDL CK VDD
/RAS /CK ODT
/CAS /CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC A13
(Top view)
Note: ( )* marked pins are for ×4 organization.
Pin name
Function
A0 to A13
Address inputs
BA0, BA1
Bank select
DQ0 to DQ15
DQS, /DQS
UDQS, /UDQS
LDQS, /LDQS
RDQS, /RDQS
Data input/output
Differential data strobe
Differential data strobe for read
/CS
Chip select
/RAS, /CAS, /WE
Command input
CKE
Clock enable
CK, /CK
Differential clock input
DM, UDM, LDM
Write data mask
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
84-ball FBGA (µBGA)
(×16 organization)
1
2
3
7
8
9
A
VDD NC VSS
B
DQ14 VSSQ UDM
C
VDDQ DQ9 VDDQ
D
DQ12 VSSQ DQ11
E
VDD NC VSS
F
DQ6 VSSQ LDM
G
VDDQ DQ1 VDDQ
H
DQ4 VSSQ DQ3
J
VDDL VREF VSS
K
CKE /WE
L
NC BA0 BA1
M
A10 A1
N
VSS A3 A5
P
A7 A9
R
VDD A12 NC
VSSQ /UDQS VDDQ
UDQS VSSQ DQ15
VDDQ DQ8 VDDQ
DQ10 VSSQ DQ13
VSSQ /LDQS VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
VSSDL CK VDD
/RAS /CK ODT
/CAS /CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC NC
(Top view)
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*¹
NU*²
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
Data Sheet E0323E90 (Ver. 9.0)
3