EBS11RC4ACNA Datasheet, PDF (4/15 Pages) Elpida Memory – 1 GB Registered SDRAM DIMM

EBS11RC4ACNA
Serial PD Matrix*¹
Byte No. Function described
0
Number of bytes used by module
manufacturer
1
Total SPD memory size
2
Memory type
3
Number of row addresses bits
4
Number of column addresses bits
5
Number of banks
6
Module data width
7
Module data width (continued)
8
Module interface signal levels
SDRAM cycle time
9
(highest /CAS latency)
7.5ns
SDRAM access from Clock
10
(highest /CAS latency)
5.4ns
11
Module configuration type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
1 0 0 0 0 0 0 0 80H
0 0 0 0 1 0 0 0 08H
0 0 0 0 0 1 0 0 04H
0 0 0 0 1 1 0 1 0DH
0 0 0 0 1 0 1 1 0BH
0 0 0 0 0 0 1 0 02H
0 1 0 0 1 0 0 0 48H
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 0 0 1 01H
0 1 1 1 0 1 0 1 75H
0 1 0 1 0 1 0 0 54H
0 0 0 0 0 0 1 0 02H
12
Refresh rate/type
1 0 0 0 0 0 1 0 82H
13
SDRAM width
0 0 0 0 0 1 0 0 04H
14
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
SDRAM device attributes:
15
minimum clock delay for back-to- 0 0 0 0 0 0 0 1 01H
back random column addresses
16
SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0FH
17
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 0 0 0 1 1 0 06H
19
SDRAM device attributes:
/CS latency
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 0 1 01H
21
SDRAM device attributes
0 0 0 1 1 1 1 0 1FH
22
SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH
SDRAM cycle time
23
(2nd highest /CAS latency)
(-7A) 7.5ns
0 1 1 1 0 1 0 1 75H
(-75) 10ns
1 0 1 0 0 0 0 0 A0H
SDRAM access from Clock
24
(2nd highest /CAS latency)
(-7A) 5.4ns
0 1 0 1 0 1 0 0 54H
(-75) 6ns
0 1 1 0 0 0 0 0 60H
SDRAM cycle time
25
(3rd highest /CAS latency)
Undefined
0 0 0 0 0 0 0 0 00H
Comments
128
256 byte
SDRAM
13
11
2
72 bit
0 (+)
LVTTL
CL = 3*⁵
ECC
Normal
(7.8125µs)
Self refresh
64M × 4
×4
1 CLK
1, 2, 4, 8
4
2, 3
0
0
Registered
VDD ± 10%
CL = 2*⁵
Data Sheet E0106E30 (Ver. 3.0)
4