EDE5108AHSE Datasheet, PDF (37/81 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5108AHSE, EDE5116AHSE
Current state
/CS /RAS /CAS /WE Address
Command Operation
Note
Extended Mode H
×
×
×
×
DESL
Nop -> Enter idle after tMRD
register accessing L
H
H
H
×
NOP
Nop -> Enter idle after tMRD
L
H
L
H
BA, CA, A10 (AP)
READ/READA ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRIT/WRITA ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA
PRE
ILLEGAL
E_L
L
H
L
A10 (AP)
PALL
ILLEGAL
L
L
L
H
×
REF
ILLEGAL
L
L
L
H
×
SELF
ILLEGAL
OL
L
L
L
BA, MRS-OPCODE MRS
ILLEGAL
L
L
L
L
BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL
Remark: H = VIH. L = VIL. × = VIH or VIL
L ^{Notes: 1. This command may be issued for other banks, depending on the state of the banks.}
2. All banks must be in "IDLE".
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruptions at other timings are illegal.
5. Available in case tRCD is satisfied by AL setting.
6. Available in case tWTR is satisfied.
7. The DDR2 SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge
P _{enabled,or a write with auto-precharge enabled, may be followed by any column command to other}
banks, as long as that command does not interrupt the read or write data transfer, and all other related
limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.)
r _{The minimum delay from a read or write command with auto precharge enabled, to a command to a}
different bank, is summarized below.
o _{From command}
To command (different bank, non-
interrupting command)
Minimum delay
(Concurrent AP supported)
Units
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
(BL/2) + 2
tCK
d _{Precharge or Activate}
1
tCK
Write w/AP
Read or Read w/AP
(CL − 1) + (BL/2) + tWTR
tCK
Write or Write w/AP
BL/2
tCK
uct ^{Precharge or Activate}
1
tCK
Preliminary Data Sheet E0908E40 (Ver. 4.0)
37