EDE5108AHSE Datasheet, PDF (1/81 Pages) Elpida Memory – 512M bits DDR2 SDRAM

PRELIMINARY DATA SHEET
E EEDDE5E51511210M68AAbHHiSStEsE(D(362D4MMRww2ooSrrddDssR××A186Mbbititss)) Specifications
• Density: 512M bits
• Organization
O⎯ 16M words × 8 bits × 4 banks (EDE5108AHSE)
⎯ 8M words × 16 bits × 4 banks (EDE5116AHSE)
• Package
⎯ 60-ball FBGA (EDE5108AHSE)
⎯ 84-ball FBGA (EDE5116AHSE)
L _{⎯ Lead-free (RoHS compliant)}
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps/533Mbps/400Mbps
(max.)
• 1KB page size (EDE5108AHSE)
P ⎯ Row address: A0 to A13
⎯ Column address: A0 to A9
• 2KB page size (EDE5116AHSE)
⎯ Row address: A0 to A12
r _{⎯ Column address: A0 to A9}
• Four internal banks for concurrent operation
o ^{• Interface: SSTL_18}
• Burst lengths (BL): 4, 8
• Burst type (BT):
⎯ Sequential (4, 8)
d _{⎯ Interleave (4, 8)}
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
u _{• Driver strength: normal/weak}
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
c ^{⎯ Average refresh period}
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
t ^{• Operating case temperature range}
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
⎯ TC = 0°C to +95°C
Document No. E0908E40 (Ver. 4.0)
Date Published December 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in June, 2010.
©Elpida Memory, Inc. 2006