M2S56D20ATP Datasheet, PDF (36/41 Pages) Elpida Memory – 256M Double Data Rate Synchronous DRAM

DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column access is
allowed. tWR is referenced from the first positive CLK edge after the last data input.
/CLK
CLK
Command
A0-9,11
A10
BA0,1
DM
QS
DQ
Write Interrupted by Precharge (BL=8, CL=2.5)
WRITE
Yi
0
00
PRE
00
tWR
Dai0 Dai1
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