M2S56D20ATP Datasheet, PDF (31/41 Pages) Elpida Memory – 256M Double Data Rate Synchronous DRAM

DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by the new Read command issued to any other bank.
Random column access is allowed. READ to READ interval is 1CLK as the minimum.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
READ READ
READ
READ
A0-9,11
Yi Yj
Yk
Yl
A10
00
0
0
BA0,1
00 00
10
01
DQS
DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is 1 CLK
minimum. The time between PRE command to output disable is equal to the CAS Latency. As a result,
READ to PRE interval determines valid data length to be outputted. The figure below shows the examples of
BL=8.
/CLK
CLK
Command
DQS
DQ
Read Interrupted by Precharge (BL=8)
READ
PRE
Q0 Q1 Q2 Q3 Q4 Q5
CL=2.5
Command
DQS
DQ
READ
PRE
Q0 Q1 Q2 Q3
Command
DQS
DQ
READ PRE
Q0 Q1
31