EDE1108AFBG Datasheet, PDF (36/78 Pages) Elpida Memory – 1G bits DDR2 SDRAM

EDE1108AFBG
8. The minimum delay from the read, write and precharge command to the precharge command to the same
bank is summarized below.
[Precharge and Auto Precharge Clarification]
From command To command
Minimum delay between “From
command” to “To command“
Units
Notes
Read
Precharge (to same bank as read)
AL + (BL/2) + Max.(RTP, 2) − 2
tCK
a, b
Precharge all
AL + (BL/2) + Max.(RTP, 2) − 2
tCK
a, b
Read w/AP
Precharge (to same bank as read w/AP) AL + (BL/2) + Max.(RTP, 2) − 2
tCK
a, b
Precharge all
AL + (BL/2) + Max.(RTP, 2) − 2
tCK
a, b
Write
Precharge (to same bank as write)
WL + (BL/2) + tWR
tCK
b
Precharge all
WL + (BL/2) + tWR
tCK
b
Write w/AP
Precharge (to same bank as write w/AP) WL + (BL/2) + WR
tCK
b
Precharge all
WL + (BL/2) + WR
tCK
b
Precharge
Precharge (to same bank as precharge) 1
tCK
b
Precharge all
1
tCK
b
Precharge all
Precharge
1
tCK
b
Precharge all
1
tCK
b
a. RTP[cycles] = RU{ tRTP[ns] / tCK[ns] }, where RU stands for round up.
tCK(avg) should be used in place of tCK for DDR2-667/800.
b. For a given bank, the precharge period should be counted from the latest precharge command, either one
bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP
depending on the latest precharge command issued to that bank.
Preliminary Data Sheet E1430E20 (Ver. 2.0)
36