EDX5116ADSE Datasheet, PDF (35/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

Figure 18 Configuration (CFG) Register
7
6
rsrv
5
4
3
rsrv ^SLE rsrv
2
1
0
WIDTH[2:0]
EDX5116ADSE
Configuration Register
SADR[7:0]: 00000010₂
Read/write register
CFG[7:0] resets to 00000100₂
WIDTH[2:0] - Device interface width field.
000₂ - Reserved.
001₂ - Reserved.
010₂ - x4 device width
011₂ - x8 device width
100₂ - x16 device width
101₂, 110₂, 111₂ - Reserved
SLE - Serial Load enable field.
0₂ - WDSL-path-to-memory disabled
1₂ - WDSL-path-to-memory enabled
Figure 19 Power Management (PM) Register
7
6
5
PST[1:0]
4
3
2
reserved
1
0
PX
Power Management Register
SADR[7:0]: 00000011₂
Read/write register
PM[7:0] resets to 00000000₂
PX - Powerdown exit field.(write-one-only, read=zero)
0₂ - Powerdown entry - do not write zero - use PDN command
1₂ - Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
00₂ - Powerdown (with self-refresh)
01₂ - Active/active-idle
10₂ - reserved
11₂ - reserved
Figure 20 Write Data Serial Load (WDSL) Control Register
7
6
5
4
3
2
1
0
WDSD[7:0]
Write Data Serial Load Control Register Read/write register
SADR[7:0]: 00000100₂
WDSL[7:0] resets to 00000000₂
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 2). Writing to this register “2x16” times accumulates a full
“t_CC” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 18) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shifting
order of the write data is shown in Table 10.
Data Sheet E1033E40 (Ver. 4.0)
35