EDX5116ADSE Datasheet, PDF (1/78 Pages) Elpida Memory – 512M bits XDR™ DRAM

DATA SHEET
512M bits XDR^™ DRAM
EDX5116ADSE (32M words × 16 bits)
Overview
The EDX5116ADSE is a 512M bits XDR^™ DRAM organized
as 32M words × 16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
nology permits 4000/3200 Mb/s transfer rates while using
conventional system and board design technologies. XDR
DRAM devices are capable of sustained data transfers of
8000/6400 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
It is packaged in 104-ball FBGA compatible with Rambus
XDR DRAM pin configuration.
Features
• Highest pin bandwidth available
4000/3200 Mb/s Octal Data Rate (ODR) Signaling
• Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
• On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
• Highest sustained bandwidth per DRAM device
• 8000/6400 MB/s sustained data rate
• Eight banks: bank-interleaved transactions at full
bandwidth
• Dynamic request scheduling
• Early-read-after-write support for maximum efficiency
• Zero overhead refresh
• Dynamic width control
• EDX5116ADSE supports × 16, × 8 and × 4 mode
• Low latency
• 2.0/2.5 ns request packets
• Point-to-point data interconnect for fastest possible
flight time
• Support for low-latency, fast-cycle cores
• Low power
• 1.8V Vdd
• Programmable small-swing I/O signaling (DRSL)
• Low power PLL/DLL design
• Powerdown self-refresh support
• Per pin I/O powerdown for narrow-width operation
Pin Configuration
L
KJ H G F E
1
DQN3 DQN9 VDD GND VDD Row GND
2
1 2 3 45
DQ3 DQ9 VDD
P 3 _{DQN15 DQDNQ55 VDDDQN5RQ10 CFM}
RSRV
N 4 _{DQ15 DGQN5D GNDVDDRQ11 CFMN}
RSRV
M 5
VDD
VDDQD1 VTEDRQMN1
VDD
6
L
GND
GGNDND
RQ10GND _{GND GND VDD}
7
K
VDD RQ8
8
J
VDD RQ6
9
H
VREF RQ4
10
G
GND RQ2
11 F _{GND VTEVRDMD}
RQ0 _{GND VDD}
E 12 _VDD
GND RST
GND GND
D 13 _{DQN7 DQNSD130 VDDCMDRQ9 RQ7}
C 14
DQ7
DQ0
DQ13
CMDDQN0RQ8
RQ6
B 15
DQN11
GND
DQN1
SCKVDD
A 16 _DQ11
DQ4
DQ1
GNDDQN4VDD
VDD
GND
VDD
GND
VREF
RQ5
GND
D
CB
A
VDD SDI DQN8 DQN2
67
GND DQ8 DQ2
RDQQ4N7 RQD0Q7 DQN4 DQN14
VRTQE3RM _{GNGDND DQ4 DQ14}
DQN3 _{VTEDRQM3 VDD VDD}
VRDQD11 ^GND GND GND
RQ9 VDD
RQ7 GND
CFMN CFM
RQ5 GND
VRDQD3
VDDVTERM _GND
RQ1 GND
GND GND VDD
RSQC1K VDSDD1DQN12 DQN6
DQN2 DG2
RQ2 GND DQ12 DQ6
VTERM GND
RST DQN0 DQN10
DQN6 DQ6
VDD SDO DQ0 DQ10
A16
A8
Top view of package
Doc. No. E1033E40 (Ver. 4.0)
Date Published September 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2007-2009