EDD1216AJTA-4 Datasheet, PDF (35/50 Pages) Elpida Memory – 128M bits DDR SDRAM

EDD1216AJTA-4
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
2. Same
Different —
—*¹
3. Different Any
ACTIVE
IDLE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*¹
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
READ
1 cycle
CL=3
NOP
DM
DQ
DQS
in0 in1 in2
out0 out1 out2 out3
Data masked
[WRITE to READ delay = 1 clock cycle]
High-Z
High-Z
BL = 4
CL = 3
Preliminary Data Sheet E1031E10 (Ver. 1.0)
35