EDD1216AJTA-4 Datasheet, PDF (1/50 Pages) Elpida Memory – 128M bits DDR SDRAM

PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1216AJTA-4 (8M words × 16 bits)
Specifications
• Density: 128M bits
• Organization
⎯ 2M words × 16 bits × 4 banks
• Package: 66-pin plastic TSOP (II)
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.6V ± 0.1V
• Data rate: 500Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E1031E10 (Ver. 1.0)
Date Published March 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2007