EDS51321DBH-TS Datasheet, PDF (32/51 Pages) Elpida Memory – 512M bits Mobile RAM™ WTR (Wide Temperature Range)

EDS51321DBH-TS
Read Command to Write Command Interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set high so that the output buffer becomes high-Z before data input.
CLK
Command
READ WRIT
CL=2
DQM
CL=3
DQ (input)
DQ (output)
in B0 in B1 in B2 in B3
High-Z
READ to WRITE Command Interval (1)
BL = 4
Burst write
CLK
Command
DQM
CL=2
DQ
CL=3
READ
WRIT
2 clock
out out out in in in in
out out in in in in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set high so that the output
buffer becomes high-Z before data input.
Preliminary Data Sheet E1415E21 (Ver. 2.1)
32