EDS2532EEBH-9ATT Datasheet, PDF (32/50 Pages) Elpida Memory – 256M bits SDRAM WTR (Wide Temperature Range)

EDS2532EEBH-9ATT
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
CL=2
DQM
CL=3
DQ (input)
E _{DQ (output)}
O _CLK
L^Command
READ WRIT
in B0 in B1 in B2 in B3
High-Z
READ to WRITE Command Interval (1)
READ
WRIT
BL = 4
Burst write
DQM
CL=2
DQ
CL=3
2 clock
out out out in in in in
out out in in in in
P_{READ to WRITE Command Interval (2)}
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
r 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
oduct ^{output buffer becomes High-Z before data input.}
Data Sheet E0821E20 (Ver. 2.0)
32