ECS2532AACN-A Datasheet, PDF (29/46 Pages) Elpida Memory – 256M bits SDRAM Bare Chip

ECS2532AACN-A
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
ACT
Address
Row
WRIT WRIT
Column A Column B
BS
DQ
in A0 in B0 in B1 in B2 in B3
E Bank0
Active
Column =A Column =B
Write
Write
Burst Write Mode
BL = 4
Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
O2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
L _{command has priority.}
CLK
Command
P Address
ACT
Row 0
ACT WRIT WRIT
Row 1 Column A Column B
BS
DQ
in A0 in B0 in B1 in B2 in B3
r _Bank0
oduct ^Active
Bank3 Bank0 Bank3
Active Write Write
WRITE to WRITE Command Interval (different bank)
Burst Write Mode
BL = 4
Data Sheet E0416E50 (Ver. 5.0)
29