ECS2532AACN-A Datasheet, PDF (1/46 Pages) Elpida Memory – 256M bits SDRAM Bare Chip

DATA SHEET
256M bits SDRAM Bare Chip
ECS2532AACN-A (8M words × 32 bits) _{Specifications}
• Density: 256M bits
• Organization
⎯ 2M words × 32 bits × 4 banks
E• Package: Bare chip
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 133MHz (max.)
• 2KB page size
O⎯ Row address: A0 to A11
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
L _{• Burst type (BT):}
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
P ^access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
r ^{• Operating ambient temperature range}
oduct ^{⎯ TA=0°Cto+70°C}
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
Document No. E0416E50 (Ver. 5.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003-2005