EDS1208AATA Datasheet, PDF (15/49 Pages) Elpida Memory – 128M bits SDRAM

EDS1208AATA
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after tRP
L
H
L
H
L
H
L
H
L
L
L
L
E_L
L
L
L
Idle
H
×
O_L
H
L
H
L
H
L^L
H
L
L
L
L
L
L
L
L
Row active
H
×
L
H
L
H
L
H
L
H
L
L
Read
L
L
L
L
L
L
H
×
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
×
NOP
Enter IDLE after tRP
H
L
×
BST
ILLEGAL
L
H
BA, CA, A10 READ/READA
ILLEGAL*³
L
L
BA, CA, A10 WRIT/WRITA
ILLEGAL*³
H
H
BA, RA
ACT
ILLEGAL*³
H
L
BA, A10
PRE, PALL
NOP*⁵
L
H
×
REF, SELF
ILLEGAL
L
L
MODE
MRS
ILLEGAL
×
×
×
DESL
NOP
H
H
×
NOP
NOP
H
L
×
BST
ILLEGAL
L
H
BA, CA, A10 READ/READA
ILLEGAL*⁴
L
L
BA, CA, A10 WRIT/WRITA
ILLEGAL*⁴
H
H
BA, RA
ACT
Bank and row active
H
L
BA, A10
PRE, PALL
NOP
L
H
×
L
L
MODE
REF, SELF
MRS
Refresh
Mode register set*⁸
×
×
×
DESL
NOP
P_H
H
×
NOP
NOP
H
L
×
BST
ILLEGAL
L
H
BA, CA, A10 READ/READA
Begin read*⁶
r^L
L
BA, CA, A10 WRIT/WRITA
Begin write*⁶
H
H
BA, RA
o _H
L
BA, A10
ACT
PRE, PALL
Other bank active
ILLEGAL on same bank*²
Precharge*⁷
L
H
×
REF, SELF
ILLEGAL
L
L
MODE
MRS
ILLEGAL
d ×
×
×
DESL
Continue burst to end
H
H
×
NOP
Continue burst to end
H
L
×
BST
Burst stop
u L
H
BA, CA, A10 READ/READA
Continue burst read to /CAS
latency and New read
L
L
BA, CA, A10 WRIT/WRITA
Term burst read/start write
H
H
BA, RA
ACT
Other bank active
ILLEGAL on same bank*²
c _H
L
BA, A10
PRE, PALL
Term burst read and Precharge
L
H
×
REF, SELF
ILLEGAL
t ^L
L
MODE
MRS
ILLEGAL
Preliminary Data Sheet E0660E20 (Ver. 2.0)
15