EDS1208AATA Datasheet, PDF (1/49 Pages) Elpida Memory – 128M bits SDRAM

PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1208AATA (16M words × 8 bits) _{Specifications}
• Density: 128M bits
• Organization
 4M words × 8 bits × 4 banks
E• Package: 54-pin plastic TSOP (II)
 Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 133MHz (max.)
O• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
L _{ Interleave (1, 2, 4, 8)}
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
P ^{• Refresh cycles: 4096 cycles/64ms}
 Average refresh period: 15.6µs
• Operating ambient temperature range
 TA = 0°C to +70°C
r _Features
• Single pulsed /RAS
o _{• Burst read/write operation and burst read/single write}
operation capability
duct ^{• Byte control by DQM}
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
(Top view)
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
A0 to A11
BA0, BA1
DQ0 to DQ7
/CS
/RAS
/CAS
/WE
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0660E20 (Ver. 2.0) _{This Product became EOL in November, 2006.}
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005