EDJ4216BASE Datasheet, PDF (136/146 Pages) Elpida Memory – 4G bits DDR3 SDRAM

EDJ4216BASE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11
CK
/CK
Command
WRS4
ODTLcnw
ODT
ODTH4
ODTLon
tAON (min.)
ODTLoff
tADC (min.)
tAOF (min.)
RTT
RTT_WR
tADC (max.)
ODTLcwn4
RTT_Nom
tADC (max.)
tAOF (max.)
DQS, /DQS
DQ
in in in in
0 123
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for a Duration of 6 Clock Cycles, Example for BC4 (via MRS or OTF), AL = 0, CWL = 5.
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied;
ODT registered low at T5 would also be legal.
T0
CK
/CK
Command
ODT
RTT
T1
T2
T3
WRS4
ODTLcnw
ODTH4
ODTLon
T4
T5
T6
T7
tAON (min.)
ODTLoff
RTT_WR
tADC (max.)
T8
T9
tAOF (min.)
tAOF (max.)
DQS, /DQS
ODTLcwn4
DQ
in in in in
0 123
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for Duration of 4 Clock Cycles
Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied.
Data Sheet E1646E41 (Ver. 4.1)
136