EDJ4216BASE Datasheet, PDF (129/146 Pages) Elpida Memory – 4G bits DDR3 SDRAM

EDJ4216BASE
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination
resistance for each DQ, DQS, /DQS and DM via the ODT control pin. For ×16 configuration ODT is applied to each
DQU, DQL, DQSU, /DQSU, DQSL, /DQSL, DMU and DML signal via the ODT control pin. The ODT feature is
designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn
on/off termination resistance for any or all DRAM devices.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in figure Functional Representation of ODT.
To other
circuitry
like
RCV, ...
ODT
VDDQ/2
RTT
Switch
DQ, DQS, DM
Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control
information, see below. The value of RTT is determined by the settings of Mode Register bits (see MR1
programming figure in the section Programming the Mode Register). The ODT pin will be ignored if the Mode
Register MR1 is programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 bits A2 or A6 or A9 are non-zero. In this case the value of RTT is
determined by the settings of those bits.
Application: Controller sends WRIT command together with ODT asserted.
• One possible application: The rank that is being written to provide termination.
• DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
• DRAM does not use any write or read command decode information
• The Termination Truth Table is shown in the Termination Truth Table
[Termination Truth Table]
ODT pin
DRAM Termination State
0
OFF
1
ON, (OFF, if disabled by MR1 bits A2, A6 and A9 in general)
Data Sheet E1646E41 (Ver. 4.1)
129