EBD52UC8AAFA Datasheet, PDF (13/18 Pages) Elpida Memory – 512MB Unbuffered DDR SDRAM DIMM

EBD52UC8AAFA
Timing Parameter Measured in Clock Cycle for unbuffered DIMM
Number of clock cycle
Parameter
Symbol
min.
max.
Unit
Write to pre-charge command delay (same bank)
tWPD
3 + BL/2
tCK
Read to pre-charge command delay (same bank)
tRPD
BL/2
tCK
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
(CL = 2)
E(CL = 2.5)
Read command to write command delay
(to output all data)
(CL = 2)
(CL = 2.5)
O_{Pre-charge command to High-Z}
(CL = 2)
(CL = 2.5)
L ^{Write command to data in latency}
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
2 + BL/2
2
3
2
2
2.5
2.5
2 + BL/2
3 + BL/2
2
2
2.5
2.5
1
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Write recovery
DM to data in latency
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down exit to command input
tWR
2
tCK
tDMD
0
0
tCK
tMRD
2
tCK
tSNR
75
tCK
tSRD
200
tCK
Product _tPDEX
1
tCK
Data Sheet E0362E20 (Ver. 2.0)
13