EDS1232AATA-75L-E Datasheet, PDF (11/53 Pages) Elpida Memory – 128M bits SDRAM (4M words x 32 bits)

EDS1232AATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
CLK
CKE _H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Row
Add
Row
Row Address Strobe and Bank Activate Command
Data Sheet E0386E40 (Ver. 4.0)
11