EDS6416AHBH Datasheet, PDF (1/49 Pages) Elpida Memory – 64M bits SDRAM (4M words x 16 bits)

DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH
(4M words × 16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64M bits
SDRAMs organized as 1,048,576 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS6416AHBH) and 2.5V
(EDS6416CHBH).
It is packaged in 60-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
 RoHS compliant
Pin Configurations
/xxx indicate active low signal.
60-ball FBGA
1
2
3
4
5
6
7
A
VSS DQ15
B
DQ14 VSSQ
C
DQ13 VDDQ
D
DQ12 DQ11
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
E
DQ10 VSSQ
VDDQ DQ5
F
DQ9 VDDQ
G
DQ8 NC
VSSQ DQ6
NC DQ7
H
NC VSS
J
NC UDQM
VDD NC
LDQM /WE
K
NC CLK
L
CKE NC
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
/RAS /CAS
NC /CS
BA1 BA0
A0 A10
A2 A1
A3 VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0442E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005