EDK1216CFBJ Datasheet, PDF (1/56 Pages) Elpida Memory – 128M bits DDR Mobile RAM™

PRELIMINARY DATA SHEET
128M bits DDR Mobile RAM
EDK1216CFBJ (8M words × 16 bits)
Specifications
• Density: 128M bits
• Organization
 2M words × 16 bits × 4 banks
• Package: 60-ball FBGA
 Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.7V to 1.95V
• Clock frequency: 133MHz (max.)
• 1KB page size
 Row address: A0 to A11
 Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 2, 4, 8, 16
• Burst type (BT):
 Sequential (2, 4, 8, 16)
 Interleave (2, 4, 8, 16)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, 1/2, 1/4, 1/8
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
 Average refresh period: 15.6µs
• Operating ambient temperature range
 TA =−25°C to +85°C
Features
• Low power consumption
• Partial Array Self-Refresh (PASR)
• Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
• Double-data-rate architecture; two data transfers per
one clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Burst termination by burst stop command and
Precharge command
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1 2 3 4 5 6 7 8 9 10
A
VSS DQ15 VSSQ
B
VDDQ DQ13 DQ14
C
VSSQ DQ11 DQ12
D
VDDQ DQ9 DQ10
E
VSSQ UDQS DQ8
F
VSS UDM NC
G
CKE CK /CK
H
A9 A11 NC
J
A6
A7
A8
K
VSS A4
A5
VDDQ DQ0 VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 VSSQ
DQ7 LDQS VDDQ
NC LDM VDD
/WE /CAS /RAS
/CS BA0 BA1
A10 A0
A1
A2 A3 VDD
(Top View)
A0 to A11
BA0, BA1
DQ0 to DQ15
UDQS, LDQS
/CS
/RAS
/CAS
/WE
UDM, LDM
CK
/CK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Write data mask
Clock input
Differential clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E1194E20 (Ver. 2.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2009