EDE5116AJSE-LI Datasheet, PDF (1/76 Pages) Elpida Memory – 512M bits DDR2 SDRAM

DATA SHEET
512M bits DDR2 SDRAM
WTR (Wide Temperature Range)
EDE5116AJSE-LI (32M words × 16 bits) _{Specifications}
• Density: 512M bits
E• Organization
 8M words × 16 bits × 4 banks
• Package
 84-ball FBGA
O^{ Lead-free (RoHS compliant)}
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 667Mbps (max.)
• 2KB page size
L ^{ Row address: A0 to A12}
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
 Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
P ^{ Sequential (4, 8)}
 Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
r _{• Driver strength: normal/weak}
• Refresh: auto-refresh, self-refresh
o _{• Refresh cycles: 8192 cycles/64ms}
 Average refresh period: 7.8µs
• Operating case temperature range
duct ^{ TC = -40°C to +95°C}
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• Wide temperature range
 TC = −40°C to +95°C
Document No. E1171E40 (Ver. 4.0)
Date Published July 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2010.
Elpida Memory, Inc. 2007-2008