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EDE2108AEBG Datasheet, PDF (1/73 Pages) Elpida Memory – Lead-free (RoHS compliant) and Halogen-free | |||
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DATA SHEET
2G bits DDR2 SDRAM
EDE2108AEBG (256M words ï´ 8 bits)
Specifications
ï· Density: 2G bits
ï· Organization
ï¾ 32M words ï´ 8 bits ï´ 8 banks
ï· Package
ï¾ 60-ball FBGA
ï¾ Lead-free (RoHS compliant) and Halogen-free
ï· Power supply: VDD, VDDQ ï½ 1.8V ï± 0.1V
ï· Data rate
ï¾ 800Mbps (max.)
ï· 1KB page size
ï¾ Row address: A0 to A14
ï¾ Column address: A0 to A9
ï· Eight internal banks for concurrent operation
ï· Interface: SSTL_18
ï· Burst lengths (BL): 4, 8
ï· Burst type (BT):
ï¾ Sequential (4, 8)
ï¾ Interleave (4, 8)
ï· /CAS Latency (CL): 3, 4, 5, 6
ï· Precharge: auto precharge option for each burst
access
ï· Driver strength: normal, weak
ï· Refresh: auto-refresh, self-refresh
ï· Refresh cycles: 8192 cycles/64msï
ï¾ Average refresh period
7.8ïs at 0ï°C ï£ TC ï£ ï«85ï°C
3.9ïs at ï«85ï°C ï¼ TC ï£ ï«95ï°C
ï· Operating case temperature range
ï¾ TC = 0ï°C to +95ï°C
Features
ï· Double-data-rate architecture; two data transfers per
clock cycle
ï· The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
ï· Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
ï· DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
ï· Differential clock inputs (CK and /CK)
ï· DLL aligns DQ and DQS transitions with CK
transitions
ï· Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
ï· Data mask (DM) for write data
ï· Posted /CAS by programmable additive latency for
better command and data bus efficiency
ï· /DQS can be disabled for single-ended Data Strobe
operation
ï· Off-Chip Driver (OCD) impedance adjustment is not
supported.
Document No. E1950E11 (Ver.1.1)
Date Published December 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
ï£Elpida Memory, Inc. 2012
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