EDD2508AKTA-5-E Datasheet, PDF (1/48 Pages) Elpida Memory – 256M bits DDR SDRAM (32M words x 8 bits, DDR400)

PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AKTA-5-E (32M words × 8 bits, DDR400)
Description
Pin Configurations
The EDD2508AKTA-5 is a 256M bits DDR SDRAM
organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Features
• Power supply: VDD, VDDQ = 2.6V ± 0.1V
• Data rate: 400Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
NC 4
DQ1 5
VSSQ 6
NC 7
DQ2 8
VDDQ 9
NC 10
DQ3 11
VSSQ 12
NC 13
NC 14
VDDQ 15
NC 16
NC 17
VDD 18
NC 19
NC 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
66 VSS
65 DQ7
64 VSSQ
63 NC
62 DQ6
61 VDDQ
60 NC
59 DQ5
58 VSSQ
57 NC
56 DQ4
55 VDDQ
54 NC
53 NC
52 VSSQ
51 DQS
50 NC
49 VREF
48 VSS
47 DM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0609E20 (Ver. 2.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005