ECS1232ECCN-A Datasheet, PDF (1/48 Pages) Elpida Memory – 128M bits SDRAM Bare Chip

PRELIMINARY DATA SHEET
128M bits SDRAM Bare Chip
ECS1232ECCN-A (4M words × 32 bits) _{Specifications}
• Density: 128M bits
• Organization
 1M words × 32 bits × 4 banks
E• Package: Bare chip
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Clock frequency: 111MHz (max.)
• Four internal banks for concurrent operation
O• Interface: LVCMOS
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
 Interleave (1, 2, 4, 8)
L _{• /CAS Latency (CL): 2, 3}
• Precharge: auto precharge option for each burst
access
• Driver strength: half/quarter
• Refresh: auto-refresh, self-refresh
P ^{• Refresh cycles: 4096 cycles/64ms}
 Average refresh period: 15.6µs
• Operating ambient temperature range
roduct ^{ TA=0°Cto+70°C}
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
• 1.8V power supply
Document No. E0780E20 (Ver. 2.0) _{This product became EOL in September, 2007.}
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006