E521.40 Datasheet, PDF (83/84 Pages) ELMOS Semiconductor AG – Transceiver compliant with PSI5 standard v1.3 and v2.1

2 Channel Multi-Mode PSI5 Transceiver
Production Data – Apr 27, 2016
E521.40
6.2.4.9 Long SYNC Pulse Command..........................................................................................................52
6.2.4.10 No SYNC Pulse Command............................................................................................................52
6.2.4.11 Software Reset Command.............................................................................................................53
6.2.4.12 Response to Read Register Command.........................................................................................53
6.2.4.13 Transfer PSI5 Data........................................................................................................................54
6.2.5 XCRC[5:0] Calculation.............................................................................................................................55
6.2.6 CONFIGURATION...................................................................................................................................56
6.2.6.1 ASIC Configuration..........................................................................................................................56
6.2.6.1.1 Asynchronous mode................................................................................................................59
6.2.6.2 Timeslot Configuration.....................................................................................................................60
6.2.6.2.1 Timeslot Length.......................................................................................................................67
6.2.6.3 Error Registers.................................................................................................................................69
6.2.6.4 Diagnosis Registers.........................................................................................................................75
7 Package Information.................................................................................................................................................78
7.1 QFN20L5..........................................................................................................................................................78
7.2 SOIC20.............................................................................................................................................................79
8 Index.........................................................................................................................................................................81
Illustration Index
Figure 2.1.1-1: Application Circuit with LDO.................................................................................................................6
Figure 2.1.1-2: Application Circuit with VBUS Supplied from ECU...............................................................................7
Figure 6.1.3.5-1: Current Modulation..........................................................................................................................26
Figure 6.1.3.6-1: Sync Pulse Timing Diagram............................................................................................................27
Figure 6.1.3.7-1: Long SYNC Pulse Trigger via Pin TRIG..........................................................................................28
Figure 6.1.3.7-2: Short SYNC Pulse Trigger via Pin TRIG.........................................................................................28
Figure 6.1.3.8-1: Short SYNC Ptrigger via UART.......................................................................................................28
Figure 6.1.3.8-2: Short SYNC Pulse Trigger via SPI..................................................................................................29
Figure 6.2.2.1-1: Buffer Architecture Overview...........................................................................................................33
Figure 6.2.2.1.1-1: UART Data Buffer.........................................................................................................................34
Figure 6.2.2.1.2-1: SPI Data Buffer.............................................................................................................................35
Figure 6.2.2.1.2-2: SPI Data Buffer incl. 4 Frames.....................................................................................................35
Figure 6.2.2.2.3-1: Example MCD Duty Cycle............................................................................................................36
Figure 6.2.2.2.4-1: MD_FERR_CHx_F1.....................................................................................................................36
Figure 6.2.2.2.4-2: Set Of Error Flags (2errors; data=0x3FF).....................................................................................37
Figure 6.2.3-1: Data Flow Graphic..............................................................................................................................37
Figure 6.2.3.1-1: SPI Error Handling Example 1.........................................................................................................38
Figure 6.2.3.1-2: SPI Error Handling Example 2.........................................................................................................38
Figure 6.2.3.1-3: SPI Error Handling Example 3.........................................................................................................38
Figure 6.2.3.1-4: SPI Error Handling Example 4.........................................................................................................38
Figure 6.2.3.4-1: SPI NOP Command.........................................................................................................................42
Figure 6.2.3.5-1: SPI Write Register Command..........................................................................................................42
Figure 6.2.3.6-1: SPI Software Reset Command........................................................................................................42
Figure 6.2.3.7-1: SPI Read Register Command.........................................................................................................43
Figure 6.2.3.8-1: SPI SYNC Pulse Command.............................................................................................................43
Figure 6.2.3.9-1: Valid read sensor data window 1.....................................................................................................44
Figure 6.2.3.9-2: Valid read sensor data window 2.....................................................................................................44
Figure 6.2.3.9.1-1: SPI Read Sensor Data 16bit.........................................................................................................45
Figure 6.2.3.9.1-2: SPI Read Sensor Data 16bit-request at SDI_RXD -1st SPI frame-.............................................45
Figure 6.2.3.9.1-3: Response to SPI Read Sensor Data 16bit at SDO_TXD -2nd SPI frame-..................................45
Figure 6.2.3.9.2-1: Read Sensor Data 24bit command...............................................................................................46
Figure 6.2.3.9.3-1: Read Sensor Data 32bit command...............................................................................................46
Figure 6.2.3.9.4-1: Read Sensor Data 48bit command...............................................................................................46
Figure 6.2.4.1-1: UART Error Handling Example 1.....................................................................................................47
Figure 6.2.4.1-2: UART Error Handling Example 2.....................................................................................................47
Figure 6.2.4.1-3: Syncpulse staggering.......................................................................................................................48
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
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QM-No.: 25DS0110E.04