E521.41 Datasheet, PDF (63/89 Pages) ELMOS Semiconductor AG – Transceiver compliant with PSI5 standard v1.3 and v2.1

4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Register Name Address
Description
CH4_CFG1
0x18 Channel 4 Configuration Register 1
CH4_CFG2
0x19 Channel 4 Configuration Register 2
CH4_CFG3
0x1A Channel 4 Configuration Register 3
CH4_CFG4
0x1B Channel 4 Configuration Register 4
CH4_CFG5
0x1C Channel 4 Configuration Register 5
CH4_CFG6
0x1D Channel 4 Configuration Register 6
CH4_CFG7
0x1E Channel 4 Configuration Register 7
It is highly recommended, not to change the registers CHX_CFG1(IDAC_CNT_MODE, IDAC_CNT_INC2[1:0],
IDAC_CNT_INC1[1:0]) and CHX_CFG2(IDAC_CNT_DEC2[1:0], IDAC_CNT_DEC1[1:0]) since these registers
control the Ibase tracking function!
Table 6.2.6.2-2: Register CH1_CFG1 (0x03) Channel 1 Configuration Register 1
Content
Reset value
Access
Bit Description
MSB
IDAC_ IDAC_CNT_I IDAC_CNT_I EN_E T1_C TS1_FLEN[4:0]
CNT_ NC2[1:0]
NC1[1:0]
R_CH RC
MODE
K
0
00
00
0
0
00011
R/W R/W
R/W
R/W R/W R/W
IDAC_CNT_MODE : reserved
IDAC_CNT_INC2[1:0] : reserved
IDAC_CNT_INC1[1:0] : reserved
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T1_CRC : PSI5 frame error detection mode of frames starting in timeslot 1
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS1_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 1
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved
Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3
T1_LEN[3:0] : Timeslot 1 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 4*32us = 128us
T1_LEN[3:0]
0100
R/W
LSB
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
63 / 89
QM-No.: 25DS0109E.06