E521.41 Datasheet, PDF (43/89 Pages) ELMOS Semiconductor AG – Transceiver compliant with PSI5 standard v1.3 and v2.1

4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
ChLx = Sync pulse length (0=short; 1=long)
Note:
• For 'Read Sensor Data xxbit' commands the SPI frame n+1 includes optional the 'SYNC Pulse command'
instead of NOP command to optimize the SPI bandwidth
• The idle time between consecutive SPI frames has to fulfill parameter ton_NCS.
6.2.3.3 Overview of SPI commands
All valid SPI commands are shown in the table below.
Any other combinations (commands from micro controller) are rejected but flagged in register
ERROR_STATUS_1[UART_SPI_INV_CMD] for diagnosis purpose.
In case of reset or communication error the following response will be sent: 0x0000 in the following valid SPI frame.
Execution of command is blocked.
Chip select (NCS) low without any clock pulses at SCLK will be ignored. Next response to previous valid frame.
Table 6.2.3.3-1: Overview SPI commands
SPI command
SPI_Write_Register
SPI_Read_Register
SPI_Sync_Pulse
SPI_Get_Data_16b
SPI_Get_Data_24b
SPI_Get_Data_32b
SPI_Get_Data_48b
SPI_NOP
SPI_SW_Reset
command
bits[15:12]
0001
0010
0011
0100
0101
0111
1000
1110
1111
remaining bits [11:0]
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
6.2.3.4 No Operation Command
Receiving a NOP command, the IC will perform no operation.
It shall be used to get the last frame of a SPI communication sequence.
The bit configuration of this one frame command is shown in the figure below:
MSB
SPI frame n
LSB
MSB
SPI frame n+1
LSB
SDI_RXD ^{idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle}
SP I_ N OP
Stuff
next cmd
SDO_TXD ^{idle x x x x x x x x x x x x x x x x idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle}
Response to previous cmd
S PI_ N O P
Stuff
Figure 6.2.3.4-1: SPI NOP Command
6.2.3.5 Write Configuration Register Command
With the command "Write Configuration Register" any 16bit register can be written.
Every command consists of three consecutive SPI frames, shown in the figure below.
As SPI frame n+2 on SDI_RXD are following cmds allowed: SPI_Write_Register, SPI_Read_Register,
SPI_SYNC_Pulse, SPI_NOP or a SPI_SW_Reset.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
43 / 89
QM-No.: 25DS0109E.06