GD25LQ128C Datasheet, PDF (8/62 Pages) ELM Electronics – 128M-bit Serial Flash

GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
Figure 1. Hold Condition
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CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25LQ128C provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
- Erase Security Registers / Program Security Registers
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table 1. GD25LQ128C Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
××000
00001
00010
00011
00100
00101
00110
01001
01010
01011
01100
01101
01110
Blocks
NONE
252 to 255
248 to 255
240 to 255
224 to 255
192 to 255
128 to 255
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
Addresses
NONE
FC0000H-FFFFFFH
F80000H-FFFFFFH
F00000H-FFFFFFH
E00000H-FFFFFFH
C00000H-FFFFFFH
800000H-FFFFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
000000H-7FFFFFH
Density
NONE
256KB
512KB
1MB
2MB
4MB
8MB
256KB
512KB
1MB
2MB
4MB
8MB
Portion
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
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Rev.1.0