GD25LQ128C Datasheet, PDF (43/62 Pages) ELM Electronics – 128M-bit Serial Flash

GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
7.28. Erase Security Registers (44H)
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The GD25LQ128C provides three 512-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command
→ CS# goes high. The command sequence is shown in Figure30. CS# must be driven high after the eighth bit
of the command code has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP
protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the
Erase Security Registers command will be ignored.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
Security Register #2
00H
Security Register #3
00H
0001
0010
0011
000
000
000
Do not care
Do not care
Do not care
Figure 30. Erase Security Registers command Sequence Diagram
CS#
SCLK
0123456789
29 30 31
Command
24 Bits Address
SI
44H
23 22
210
MSB
62 - 43
Rev.1.0