GD25Q41 Datasheet, PDF (36/46 Pages) ELM Electronics – Uniform Sector Dual and Quad Serial Flash

GD25Q41BxIGx Uniform Sector Dual and Quad Serial Flash
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Address
Security Register #1
Security Register #2
Security Register #3
A23-16
00H
00H
00H
A15-12
0001
0010
0011
A11-9
000
000
000
A8-0
Byte Address
Byte Address
Byte Address
Figure 34. Read Security Registers command Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI
SO
CS#
SCLK
SI
SO
Command
48H
High-Z
24-bit address
23 22 21
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210
Data Out1
Data Out2
76543210765
MSB
MSB
7.30. Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further
reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not
require the BBH/EBH/E7H command code.
If the system controller is reset during operation it will likely send a standard SPI command, such as Read ID
(9FH) or Fast Read (0BH), to the device. Because the GD25Q41B has no hardware reset pin, so if Continuous
Read Mode bits are set to “AXH”, the GD25Q41B will not recognize any standard SPI commands. So
Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and
allow standard SPI command to be recognized.
Figure 35. Continuous Read Mode Reset Sequence Diagram
CS#
SCLK
Mode Bit Reset for Quad/Dual I/O
01234567
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
FFH
Don`t Care
Don`t Care
Don`t Care
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Rev.1.1