GD25Q41 Datasheet, PDF (35/46 Pages) ELM Electronics – Uniform Sector Dual and Quad Serial Flash

GD25Q41BxIGx Uniform Sector Dual and Quad Serial Flash
7.28. Program Security Registers (42H)
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The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
Security Register #1
Security Register #2
Security Register #3
A23-16
00H
00H
00H
A15-12
0001
0010
0011
A11-9
000
000
000
A8-0
Byte Address
Byte Address
Byte Address
Figure 33. Program Security Registers command Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SI
CS#
SCLK
Command
42H
24-bit address
Data Byte 1
23 22 21
321076543210
MSB
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
SI
7654321076543210
76543210
MSB
MSB
MSB
7.29. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches the
last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high.
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