GD25LQ256 Datasheet, PDF (26/68 Pages) ELM Electronics – 1.8V Uniform Sector Dual and Quad Serial Flash

GD25LQ256CWIGx 1.8V Uniform Sector Dual and Quad Serial Flash
7.11. Quad Output Fast Read (6BH)
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The Quad Output Fast Read command is followed by 3-byte address (A23-A0) or a 4-byte address (A31-A0)
and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed
Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out.
Figure 12. Quad Output Fast Read Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Command
24-bit address
6BH
23 22 21
3210
High-Z
High-Z
High-Z
CS#
SCLK
SI(IO0)
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
40404040 4
SO(IO1)
515151515
WP#(IO2)
626262626
HOLD#(IO3)
737373737
Byte1 Byte2 Byte3 Byte4
Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.
7.12. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to
input the 3-byte address (A23-0) or a 4-byte address (A31-A0) and a “Continuous Read Mode” byte 2-bit per
clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure13. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address
after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0) or a 4-byte address (A31-A0). If the
“Continuous Read Mode” bits (M5-4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised
and then lowered) does not require the BBH command code. The command sequence is shown in followed
Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the
first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can
be used to reset (M5-4) before issuing normal command.
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