MA28151 Datasheet, PDF (15/22 Pages) Dynex Semiconductor – Radiation hard Programmable Communication Interface

MA28151
5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min. Max. Units
Condition
t_CY
t₀
t₀
t_R, t_F
t_DTX
t_TPW
t_TPD
t_RPW
t_RPD
t_TxRDY
t_{TxRDY CLEAR}
t_RxRDY
t_{RxRDY CLEAR}
t_TxEMPTY
t_WC
t_CR
t_AR
t_RA
t_RR
t_RD
t_DF
t_DW
t_WD
t_RV
Internal clock cycle time
External Clock high pulse width
External Clock low pulse width
Clock rise and fall time
TxD delay from falling edge of TxD
Transmitter input clock pulse width
Transmitter input clock pulse delay
Receive input clock pulse width
Receive input clock pulse delay
TxRDY pin delay from CENTER of last bit
TxRDY fall from falling DSN (WRITE)
RxRDY pin delay from center of last bit
RxRDY fall from falling DSN (READ)
TxEMPTY from centre of last bit
Control delay from rising edge of WRITE
Control to READ set-up time (DSR, CTS)
Address stable before DSN (CSN, CDN)
Address hold time before DSN (CSN, CDN)
DSN pulse width
Data delay from DSN falling (READ)
DSN rising to data floating (READ)
Data set-up time to DSN rising (WRITE)
Data hold time to DSN rising (WRITE)
Recovery time between writes (not shown)
200 1000
nS
25
-
nS
25
-
nS
-
10
nS
-
1
µS
12xt_CY
-
-
1xt_CY
-
-
15xt_CY
-
-
3xt_CY
-
-
12xt_CY
-
-
1xt_CY
-
-
15xt_CY
-
-
3xt_CY
-
-
-
8xt_CY
-
-
45
-
-
26xt_CY
-
-
45
-
20xt_CY
-
-
8xt_CY
-
-
20xt_CY
-
-
0
-
ns
0
-
ns
20
-
ns
-
30
ns
10
45
ns
15
-
ns
5
-
ns
6xt_CY
-
-
Notes 1, 5, 6
-
-
-
-
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
1 x baud rate
16 x and 64 x baud rate
Note 7
Note 7
Note 7
Note 7
Note 7
Note 7
Note 7
Note 2
Note 2
-
Note 3
Note 8
-
-
Note 4
Notes: 1. AC Timings measured V_OH = 1.5 V_OL = 1.5.
2. CSN and Command/Data are considered as addresses.
3. Assumes that address is valid before DSN goes low.
4. This recovery time is for Mode Initialisation only. Write data is allowed when TxRDY = 1. Recovery time between
writes for Asynchronous Mode is 8xt_CY and for Synchronous Mode is 16xt_CY.
5. The TxC and RxC frequencies have the following limitation with respect to clock: For 1 x baudrate, f_TX or f_RX≤1/
(30t_CY): For 16 x and 64 x baud rate, f_TX or f_RX ≤1/(4.5t_CY).
6. Reset Pulse Width = 6t_CY minimum; System clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. Data Bus connected to V_DD via loads of 680Ω (minimum).
Mil-Std-883, method 5005, subgroups 9, 10, 11
Figure 23: AC Electrical Characteristics
Symbol
Parameter
Min. Max. Units
-
Clock Frequency (osc)
-
20
MHz
f_Tx
Transmitter input clock frequency
DC
64
kHz
DC
310
kHz
DC
615
kHz
f_Rx
Receiver input clock frequency
DC
64
kHz
DC
310
kHz
DC
615
kHz
Mil-Std-883, method 5005, subgroups 7, 8A, 8B
Figure 24: Operating AC Electrical Characteristics
Condition
-
1 x baud rate
16 x baud rate
64 x baud rate
1x baud rate
16 x baud rate
64 x baud rate
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