APX809 Datasheet, PDF (4/9 Pages) Diodes Incorporated – 3-PIN MICROPROCESSOR RESET CIRCUITS

APX809/810
3-PIN MICROPROCESSOR RESET CIRCUITS
Typical Application Circuit
C_IN
100nF
V _CC
V _CC
APX8XX
RESET
(RESET)
V _CC
Microprocessor
RESET
INPUT
GND
GND
Functional Description
A microprocessor’s (µP’s) reset input starts the µP in a known
state. The APX809/810 assert reset to prevent code-execution
errors during power-up, power-down, or brownout conditions.
They assert a reset signal whenever the V_CC supply voltage
declines below a preset threshold, keeping it asserted for at least
240ms after V_CC has risen above the reset threshold. The
APX809/810 have a push-pull output stage.
Ensuring a Valid Reset Output
Down to V_CC = 0
RESET is guaranteed to be a logic low for V_CC > 1V. Once V_CC
exceeds the reset threshold, an internal timer keeps RESET
low for the reset timeout period; after this interval, RESET
goes high. If a brownout condition occurs (V_CC dips below the
RESET reset threshold), RESET goes low. Any time
V_CC goes below the reset threshold, the internal timer resets to
zero, and RESET goes low. The internal timer starts after
V_CC returns above the reset threshold, and RESET remains
low for the reset timeout period.
When V_CC falls below 1V, the APX809 RESET output no
longer sinks current—it becomes an open circuit. Therefore,
high-impedance CMOS logic inputs connected to RESET can
drift to undetermined voltages.
This presents no problem in most applications since most µP and
other circuitry is inoperative with V_CC below 1V. However, in
applications where RESET must be valid down to 0V, adding a
pull down resistor to RESET causes any stray leakage
currents to flow to ground, holding RESET low. R1’s value is
not critical; 100k are large enough not to load RESET and
small enough to pull RESET to ground. For the APX810 if
RESET is required to remain valid for V_CC < 1V.
Benefits of Highly Accurate Reset Threshold
Most µP supervisor ICs has reset threshold voltages between
5% and 10% below the value of nominal supply voltages. This
ensures a reset will not occur within 5% of the nominal supply,
but will occur when the supply is 10% below nominal. When using
ICs rated at only the nominal supply ±5%, this leaves a zone of
uncertainty where the supply is between 5% and 10% low, and
where the reset may or may not be asserted.
APX809/810 Rev. 3
4 of 9
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MARCH 2008
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